Memory device and method for operating the same
AssigneeNanya Technology Corporation
InventorKuo-Chiang Hung
Life of this patent
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Abstract
A memory device includes a first chip, a second chip and a processor. The second chip is coupled to the first chip at a first node. The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node. A method for operating a memory device is also disclosed herein.
Claims19
A memory device, comprising:
- a first chip;
- a second chip coupled to the first chip, and comprising:
- a first capacitor;
- and
- a first variable resistor coupled in series with the first capacitor;
- and
- a processor coupled to the first chip and configured to control the first variable resistor.
A method for operating a memory device, comprising:
- adjusting a first chip to a first resistance;
- after the first chip is adjusted to the first resistance, writing first data stored in a second chip into a processor;
- and
- after the first data is written into the processor, adjusting the first chip to a second resistance lower than the first resistance.
A memory device, comprising:
- a first chip configured to store first data;
- a second chip coupled to the first chip;
- and
- a processor configured to increase a resistance of the second chip and decrease a resistance of the first chip in response to reading the first data,
- wherein the second chip is configured to store second data, and
- the processor is further configured to read the second data, and configured to increase the resistance of the first chip in response to reading the second data.
Dependencies are inferred from the claim text.