Counting control circuit , method for counting control circuit and semiconductor memory with counting control circuit

A semiconductor memory, comprising a counting control circuit, wherein the counting control circuit comprises a logic control circuit and a counting statistic circuit, an output terminal of the logic control circuit is connected to a clock terminal of the counting statistic circuit,

• the logic control circuit is configured to receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under a control of the first identification signal, and
• the counting statistic circuit is configured to receive the counting clock signal, count according to the counting clock signal, and generate the first identification signal, wherein the first identification signal indicates a generation of a command signal for performing a first operation, and the first identification signal is in a valid state under a condition that a counting value meets a preset condition;
• wherein the logic control circuit comprises:
• a first driving circuit, configured to perform driving on the first clock signal, to obtain a first intermediate signal;
• and
• a first logic circuit, configured to perform a logical operation on the first intermediate signal and the first identification signal, to obtain the counting clock signal;
• wherein the first logic circuit comprises:
• a first delay inverting circuit, configured to delay and invert the first identification signal, to obtain a second intermediate signal;
• a first NAND gate, configured to perform a NAND logical operation on the first intermediate signal and the second intermediate signal, to obtain a third intermediate signal;
• and
• a second NOT gate, configured to perform a NOT logical operation on the third intermediate signal, to obtain the counting clock signal.

A counting control circuit, comprising a logic control circuit and a counting statistic circuit, an output terminal of the logic control circuit connected to a clock terminal of the counting statistic circuit,

• wherein the logic control circuit is configured to receive a first clock signal and a first identification signal, and generate a counting clock signal according to the first clock signal under a control of the first identification signal, and
• the counting statistic circuit is configured to receive the counting clock signal, count according to the counting clock signal, and generate the first identification signal, wherein the first identification signal indicates a generation of a command signal for performing a first operation, and the first identification signal is in a valid state under a condition that a counting value meets a preset condition;
• wherein the counting statistic circuit comprises a counting circuit and a decoding circuit, an output terminal of the counting circuit is connected to an input terminal of the decoding circuit,
• the counting circuit is configured to receive the counting clock signal, count according to the counting clock signal, and generate a counting signal used for characterizing the counting value,
• the decoding circuit is configured to receive the counting signal, decode the counting signal, and generate the first identification signal, wherein the first identification signal is in the valid state under the condition that the counting value meets the preset condition;
• wherein the counting circuit comprises a synchronous binary counter, the synchronous binary counter comprises a plurality of counting sub-circuits cascaded sequentially, each of the plurality of counting sub-circuits comprises a flip-flop, and a clock terminal of each flip-flop is configured to receive the counting clock signal,
• the plurality of counting sub-circuits are configured to receive the counting clock signal, perform clock sampling through flip-flops respectively comprised in the plurality of counting sub-circuits, and output the counting signal,
• the counting signal comprises a plurality of bits, and there exists one-to-one correspondences between the plurality of counting sub-circuits and the plurality of bits comprised in the counting signal.