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US 12,483,233 B2Granted
Method for suppressing voltage overshoots
AssigneeSemiconductor Components Industries, LLC
InventorsJoseph Andrew Yedinak, Gary Horst Loechelt, Xiaoli Wu
Life of this patent
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Abstract
Devices and methods are disclosed for facilitating faster switching of silicon-based and silicon carbide-based power transistors suitable for use in electric vehicles. The disclosed techniques can minimize the impact on turn-on and turn-off losses, while reducing gate voltage and drain voltage spikes during device switching. A fast/slow cell design incorporating shielded gate MOSFETs controls gate-to-drain capacitance and gate resistances to optimize suppression of voltage overshoot.
Claims20
An apparatus, comprising:
- a first multi-terminal device having a first source, a first shield, a first gate, and a first drain;
- a second multi-terminal device having a second source, a second shield, a second gate, and a second drain, wherein:
- the first drain is coupled to the second drain;
- the first gate is coupled to the second gate;
- and
- the first source is coupled to the second source;
- and
- a gate resistor coupled between the first gate and the second gate, the gate resistor configured to reduce voltage overshoot during a switching event, wherein the second shield is electrically coupled to the second gate.
5 more elements
A circuit, comprising:
- a plurality of first cells, each first cell comprising a first transistor having a first source, a first gate, and a first drain, the first transistor further configured with a first shield terminal coupled to the first source;
- a plurality of second cells, each second cell comprising a second transistor having a second source, a second gate, and a second drain, the second transistor further configured with a second shield terminal;
- a first gate bus coupled to the plurality of first cells, the first gate bus coupled to a common gate terminal through a first resistor;
- and
- a second gate bus coupled to the plurality of second cells, the second gate bus coupled to the common gate terminal through a second resistor.
2 more elements
A method, comprising:
- forming a plurality of first transistors and a plurality of second transistors in a die;
- configuring the plurality of first transistors to have lower power loss than the plurality of second transistors;
- and
- configuring the plurality of second transistors to have a greater gate RC time constant than the plurality of first transistors, including coupling respective gates of the plurality of second transistors to a common shield terminal.
1 more element
Dependencies are inferred from the claim text.