Control of skew between multiple data lanes
AssigneeSTMicroelectronics International N.V.
InventorsRupesh Singh, Ankur Bal
Life of this patent
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Abstract
Provided are a method and apparatus for controlling a skew between multiple data lanes. In the method and apparatus, a first data lane control stage controls control outputting first data over a first data lane based on a first data lane clock and a second data lane control stage controls outputting second data over a second data lane based on a second data lane clock. In the method and apparatus, a first device is associated with a system clock and is configured to generate the first and second data for outputting over the first and second data lanes. A clock control stage causes the first and second data lane clocks to be offset from each other by a fixed time duration that is an integer fraction of a cycle duration of the system clock.
Claims20
A system, comprising:
- a first data lane control stage configured to:
- control outputting first data over a first data lane based on a first data lane clock;
- a second data lane control stage configured to:
- control outputting second data over a second data lane based on a second data lane clock;
- a first device associated with a system clock and configured to generate the first and second data for outputting over the first and second data lanes;
- and
- a clock control stage including:
- a first flip-flop configured to:
- generate a first data lane clock reset signal;
- and
- output the first data lane clock reset signal to the first data lane control stage, the first data lane clock reset signal being operative to set a timing of the first data lane clock of the first data lane control stage;
- and
- a second flip-flop configured to:
- generate a second data lane clock reset signal that is offset from the first data lane clock reset signal a fixed time duration that is an integer fraction of a cycle duration of the system clock;
- and
- output the second data lane clock reset signal to the second data lane control stage, the second data lane clock reset signal being operative to set a timing of the second data lane clock of the second data lane control stage.
A device, comprising:
- a first flip-flop configured to:
- generate a first data lane clock reset signal;
- and
- output the first data lane clock reset signal to a first data lane control stage, the first data lane clock reset signal being operative to set a timing of a first data lane clock of the first data lane control stage, the first data lane clock being used to control outputting first data over a first data lane;
- and
- a second flip-flop configured to:
- generate a second data lane clock reset signal that is offset from the first data lane clock reset signal by an integer fraction of a cycle duration of a system clock;
- and
- output the second data lane clock reset signal to a second data lane control stage, the second data lane clock reset signal being operative to set a timing of a second data lane clock of the second data lane control stage, the second data lane clock being used to control outputting second data over a second data lane.
A method, comprising:
- generating a first data lane clock reset signal;
- setting a timing of a first data lane clock based on the first data lane clock reset signal;
- outputting first data over a first data lane based on the first data lane clock;
- generating a second data lane clock reset signal that is offset from the first data lane clock reset signal by an integer fraction of a cycle duration of a system clock;
- setting a timing of a second data lane clock based on the second data lane clock reset signal;
- and
- outputting second data over a second data lane based on the second data lane clock.
Dependencies are inferred from the claim text.