High performance pulse-amplitude modulation (PAM)/non-return-to-zero (NRZ) transmitter driver for high-speed wireline links

An apparatus, comprising:

• a first driver comprising first and third sets of driver slices;
• a second driver comprising second and fourth sets of driver slices;
• wherein each driver slice in the first set of driver slices is paired with a corresponding paired driver slice in the second set of driver slices by one or more respective switches, and each driver slice in the third set of driver slices is paired with a corresponding paired driver slice in the fourth set of driver slices by one or more respective switches;
• and
• a control circuit;
• wherein for each pair of driver slices in the first and second sets of driver slices:
• in a non-return-to-zero (NRZ) mode, the control circuit is to turn on the one or more respective switches to couple a first resistance of the driver slice of the first set of driver slices to a second resistance in the paired driver slice of the second set of driver slices;
• in a pulse amplitude modulation (PAM) mode with N=3 or more levels, the control circuit is to turn off the one or more respective switches to decouple the first resistance of the driver slice of the first set of driver slices from the second resistance in the paired driver slice of the second set of driver slices;
• and
• wherein for each pair of driver slice in the third and fourth sets of driver slices:
• in the NRZ mode, the control circuit is to turn on the one or more respective switches to couple a third resistance of the driver slice of the third set of driver slices to a fourth resistance in the paired driver slice of the fourth set of driver slices;
• and
• in the PAM mode, the control circuit is to turn off the one or more respective switches to decouple the third resistance of the driver slice of the third set of driver slices from the fourth resistance in the paired driver slice of the fourth set of driver slices.

An apparatus, comprising:

• a memory device to store instructions;
• and
• a processor to execute the instructions to:
• in a non-return-to-zero (NRZ) mode, turn on a first driver, turn off a second driver, and turn on one or more respective switches to pass a data signal to a transmission pad of the first driver via a first resistance of the first driver and a second resistance of the second driver while the second driver is turned off, and
• in a pulse amplitude modulation (PAM) mode with N=3 or more levels, turn on the first and second drivers, and turn off the one or more respective switches to decouple the first resistance from the second resistance, to pass most significant bits (MSBs) of a data stream to the first transmission pad via the first resistance but not the second resistance.