Slew-rate control circuit and slew-rate control method

A slew-rate control circuit, comprising:

• a proportional calculation circuit, configured to parallelly receive a plurality of first signals within a current preset period, generate a first indicating voltage according to a plurality of adjusted first signals within a previous preset period and the plurality of first signals within the current preset period, and generate a second indicating voltage according to the plurality of adjusted first signals within the previous preset period and a plurality of second signals that are inverted from the plurality of first signals within the current preset period, wherein the first indicating voltage indicates a first numerical relationship between a number of low-level adjusted first signals within the previous preset period that respectively transition into high-level first signals within the current preset period, and a number of high-level adjusted first signals within the previous preset period that respectively transition into low-level first signals within the current preset period, and the second indicating voltage indicates a second numerical relationship between the number of low-level adjusted first signals within the previous preset period that respectively transition into high-level second signals within the current preset period, and the number of high-level adjusted first signals within the previous preset period that respectively transition into low-level second signals within the current preset period;
• a logic operation circuit, coupled to the proportional calculation circuit, wherein the logic operation circuit is configured to receive the first indicating voltage and the second indicating voltage, and generate an operation result according to a numerical relationship between the first indicating voltage, and first and second reference voltages, and a numerical relationship between the second indicating voltage, and the first and second reference voltages, wherein the first reference voltage is greater than the second reference voltage;
• and
• an output adjustment circuit, coupled to the logic operation circuit, wherein the output adjustment circuit is configured to receive the operation result, and determine whether to invert the plurality of first signals within the current preset period to correspondingly generate a plurality of adjusted first signals within the current preset period according to the operation result.