Dynamic setup and hold times adjustment for memories

A method comprising:

• receiving by control circuitry, indications of one or more operating conditions utilized by at least a sequential circuit of an apparatus that cause a change in latencies of signals of an integrated circuit;
• and
• generating, by the control circuitry, a control signal based on detection of a combination of the one or more operating conditions;
• and
• receiving, by circuitry of a signal arrival adjuster, a first signal that is one of an input clock signal and an input data signal of a computing system;
• and
• conveying, to the sequential circuit by the signal arrival adjuster, one of a first version of the first signal or a second version of the first signal, wherein the second version of the first signal is delayed with respect to the first version of the first signal.

A computing system comprising:

• a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks;
• an integrated circuit configured to execute the instructions using the source data, wherein the integrated circuit comprises:
• a sequential circuit;
• control circuitry:
• and
• a signal arrival adjuster;
• and
• wherein the control circuitry is configured to:
• receive indications of one or more operating conditions utilized by at least the sequential circuit that cause a change in latencies of signals of the apparatus;
• and
• generate a control signal based on detection of a combination of the one or more operating conditions;
• and
• wherein the signal arrival adjuster comprises circuitry configured to:
• receive a first signal that is one of an input clock signal and an input data signal;
• and
• convey, to the sequential circuit, a second signal with a latency determined in part by the control signal.