US 12,444,444 B2Granted

Multi-write read-only memory array

AssigneeYield Microelectronics Corp.

InventorsYu-Ting Huang, Chi-Pei Wu

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Abstract

A multi-write read-only memory array includes word common-source lines, bit lines, and sub-memory arrays. The word common-source lines include a first word common-source line and a second word common-source line. The bit lines include a first bit line and a second bit line. Each sub-memory array includes a first memory cell coupled to the first word common-source line and the first bit line, a second memory cell coupled to the first word common-source line and the second bit line, a third memory cell coupled to the second word common-source line and the second bit line, and a fourth memory cell coupled to the second word common-source line and the first bit line.

Claims18

Dependent claims

A multi-write read-only memory array comprising:

a plurality of word common-source lines, arranged in parallel, comprising a first word common-source line and a second word common-source line;
a plurality of bit lines arranged in parallel, wherein the plurality of bit lines perpendicular to the plurality of word common-source lines comprise a first bit line and a second bit line;
and
a plurality of sub-memory arrays each coupled to two of the plurality of word common-source lines and two of the plurality of bit lines, wherein each of the plurality of sub-memory arrays comprises:
a first memory cell coupled to the first word common-source line and the first bit line;
a second memory cell coupled to the first word common-source line and the second bit line;
a third memory cell coupled to the second word common-source line and the second bit line;
and
a fourth memory cell coupled to the second word common-source line and the first bit line.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/529,115Filed 5 Dec 2023
Priority: TW 1121378223 Oct 2023
Published: US 2025/0111868 A13 Apr 2025
Granted: 14 Oct 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 7/18
Arrangements for writing information into, or reading information out from, a digital store: bit line organisation; Bit line lay-out
G11C 16/10
Auxiliary circuits, e.g. for writing into memory: programming or data input circuits

Family

US 2025/0111868 A1Pre-grant publication · published 3 Apr 2025
US 12,444,444 B2This patent

From the US filing history. Foreign family members aren’t listed.

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