Mask-programmable read only memory with electrically isolated cells

A mask-programmable read only memory (ROM), comprising:

• a first gate electrode configured to form a first word line;
• a second gate electrode configured to form a second word line;
• an isolation gate electrode disposed between the first gate electrode and the second gate electrode, the isolation gate electrode being configured to electrically isolate the first gate electrode from the second gate electrode;
• a first source region disposed adjacent to the first gate electrode;
• a second source region disposed adjacent to the second gate electrode;
• a first drain region disposed between, and overlapping with, the first gate electrode and the isolation gate electrode;
• a second drain region disposed between, and overlapping with, the isolation gate electrode and the second gate electrode;
• a first source contact disposed in a semiconductor substrate and electrically connected to the first source region;
• a second source contact disposed in the semiconductor substrate and electrically connected to the second source region;
• a first bit line contact disposed on the semiconductor substrate and electrically connected to the first drain region;
• a second bit line contact disposed on the semiconductor substrate and electrically connected to the second drain region;
• a first metal wiring connected to the first bit line contact, wherein the first metal wiring extends to overlap a portion of the first gate electrode and does not fully cross the first gate electrode, such that the first metal wiring does not overlap the first source region;
• a second metal wiring connected to the second bit line contact, wherein the second metal wiring extends to overlap the second gate electrode and does not overlap the second source region;
• a bit line configured to cross the first gate electrode, the second gate electrode, and the isolation gate electrode;
• and
• a via structure connecting the second metal wiring to the bit line, such that the via structure is electrically connected to the second drain region, the second bit line contact, the second metal wiring, and the bit line,
• wherein the bit line is disposed to overlap each of the first bit line contact, the second bit line contact, the first source contact, and the second source contact, and
• wherein there is no via structure connecting the first metal wiring to the bit line, such that there is no electrical connection between the first drain region and the bit line.