Low-power flip flop circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Chia Lai, Meng-Hung Shen, Chi-Lin Liu, Stefan Rusu, Yan-Hao Chen, Jerry Chang-Jui Kao
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Abstract
A flip-flop circuit configured to latch an input signal to an output signal is disclosed. The circuit includes a first latch circuit; and a second latch circuit coupled to the first latch circuit. In some embodiments, in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, and the first and second latch circuits each comprises at most two transistors configured to receive the clock signal.
Claims20
A flip-flop circuit configured to latch an input signal to an output signal, comprising:
- a multiplexer configured to select either a scan-in signal or a data signal as the input signal;
- a first latch circuit coupled to the multiplexer;
- a second latch circuit coupled to the first latch circuit, wherein in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, wherein the first latch circuit includes a pair of cross-coupled OR-AND-Inverter (OAI) logic gates, and the second latch circuit includes a pair of cross-coupled AND-OR-Inverter (AOI) logic gates;
- and
- a time-borrowing circuit coupled to the first latch circuit so as to delay the clock signal to the first latch circuit, and wherein the time-borrowing circuit does not delay the clock signal to the second latch circuit.
A flip-flop circuit configured to latch an input signal to an output signal, comprising:
- a multiplexer configured to:
- receive a scan-in signal at a first input,
- receive a data signal at a second input, and
- select either the scan-in signal or the data signal as the input signal;
- a first latch circuit coupled to the multiplexer;
- a second latch circuit coupled to the first latch circuit, wherein in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, wherein the first latch circuit includes a pair of cross-coupled OR-AND-Inverter (OAI) logic gates, and the second latch circuit includes a pair of cross-coupled AND-OR-Inverter (AOI) logic gates;
- and
- a time-borrowing circuit coupled to the first latch circuit so as to delay the clock signal to the first latch circuit, and wherein the time-borrowing circuit does not delay the clock signal to the second latch circuit.
A flip-flop circuit configured to latch an input signal to an output signal, comprising:
- a multiplexer configured to:
- receive a scan-in signal at a first input,
- receive a data signal at a second input,
- receive a scan enable signal at a third input, and
- select, based on a logic state of the scan enable signal, either the scan-in signal or the data signal as the input signal;
- a first latch circuit coupled to the multiplexer;
- a second latch circuit coupled to the first latch circuit, wherein in response to a clock signal, the first and second latch circuits are complementarily activated so as to latch the input signal to the output signal, wherein the first latch circuit includes a pair of cross-coupled OR-AND-Inverter (OAI) logic gates, and the second latch circuit includes a pair of cross-coupled AND-OR-Inverter (AOI) logic gates;
- and
- a time-borrowing circuit coupled to the first latch circuit so as to delay the clock signal to the first latch circuit, and wherein the time-borrowing circuit does not delay the clock signal to the second latch circuit.
Dependencies are inferred from the claim text.