Semiconductor storage device

A semiconductor storage device including first and second memory cells adjacent to each other in a first direction, the first and second memory cells being nonvolatile, comprising:

• first and second word lines extending in the first direction;
• and
• first and second bit lines extending in a second direction perpendicular to the first direction,
• wherein
• the first memory cell includes
• a first program transistor with a gate connected to the first word line, and
• a first switch transistor, provided between the first program transistor and the first bit line, with a gate connected to the second word line,
• the second memory cell includes
• a second program transistor with a gate connected to the first word line, and
• a second switch transistor, provided between the second program transistor and the second bit line, with a gate connected to the second word line,
• the first and second program transistors are nanosheet field effect transistors (FETs) having first and second nanosheets, respectively, as channel regions,
• the first and second switch transistors are nanosheet FETs having third and fourth nanosheets, respectively, as channel regions,
• the first word line includes a first gate interconnect surrounding peripheries of the first nanosheet in the first direction and a third direction perpendicular to the first and second directions and a second gate interconnect surrounding peripheries of the second nanosheet in the first direction and the third direction,
• the second word line includes a third gate interconnect surrounding peripheries of the third nanosheet in the first direction and the third direction and a fourth gate interconnect surrounding peripheries of the fourth nanosheet in the first direction and the third direction,
• the first and second nanosheets are opposed to each other in the first direction, a face of the first nanosheet on a side closer to the second nanosheet in the first direction is exposed from the first gate interconnect, and a face of the second nanosheet on a side closer to the first nanosheet in the first direction is exposed from the second gate interconnect, and
• the third and fourth nanosheets are opposed to each other in the first direction, a face of the third nanosheet on a side closer to the fourth nanosheet in the first direction is exposed from the third gate interconnect, and a face of the fourth nanosheet on a side closer to the third nanosheet in the first direction is exposed from the fourth gate interconnect.