Power semiconductor device with an auxiliary gate structure

A heterojunction chip having at least three terminals, the at least three terminals comprising a high voltage terminal, a low voltage terminal and a control terminal, wherein the heterojunction chip further comprises;

• at least one main power heterojunction transistor, wherein the at least one main power heterojunction transistor comprises an internal gate terminal, a source terminal and a drain terminal, wherein the source terminal of the at least one main power heterojunction transistor is operatively connected to the low voltage terminal and the drain terminal of the at least one main power heterojunction transistor is operatively connected to the high voltage terminal;
• an auxiliary gate circuit comprising at least one first low-voltage heterojunction transistor, wherein the auxiliary gate circuit is operatively connected to the internal gate terminal of the at least one main power heterojunction transistor and to the control terminal;
• a pull-down circuit comprising at least one non-linear element and at least one second low-voltage heterojunction transistor, the non-linear element comprising a potential divider for driving the gate terminal of the at least one second low-voltage heterojunction transistor, wherein the pull-down circuit is operatively connected to an internal gate terminal of the at least one first low-voltage heterojunction transistor and to the source terminal of the at least one main power heterojunction transistor;
• a current control circuit comprising at least one resistor, wherein the current control circuit is operatively connected to the control terminal and to the pull-down circuit;
• and
• wherein the auxiliary gate and current control circuits at least partially control a voltage and a current into the internal gate of the at least one main power heterojunction transistor;
• and
• at least one monolithically integrated component, the at least one monolithically integrated component being one or more of a DC to DC converter circuit, a voltage regulator, and a gate voltage to logic signal clamping circuit;
• wherein the gate voltage to logic signal clamping circuit is configured to receive an input signal and provide a magnitude limited output signal, wherein a magnitude of the output signal is limited to a set maximum voltage, and wherein the gate voltage to logic signal clamping circuit comprises a current source operatively connected in series between an input source and the output;
• and
• wherein the current control circuit at least partially controls a current into the pull down circuit and at least partially determines a control terminal voltage level at which the pull-down circuit actively pulls down a gate voltage of the at least one first low-voltage heterojunction transistor to clamp a voltage of the internal gate of the at least one main power heterojunction transistor.