Digital phase-locked loop and related merged duty cycle calibration scheme for frequency synthesizers

An apparatus for duty cycle error calibration, comprising:

• a multi-modulus divider (MMD) circuit with an MMD output, the MMD circuit configured to generate a first delayed clock signal by delaying a clock signal by a first time delay associated with a first range of time delays;
• a retimer circuit with a retimer input and a retimer output, the retimer input coupled to the MMD output, the retimer circuit configured to generate a second delayed clock signal by delaying the first delayed clock signal by a second time delay associated with a second range of time delays;
• and
• a digitally controlled delay line (DCDL) circuit with a DCDL input coupled to the retimer output, the DCDL circuit configured to generate a third delayed clock signal by a third time delay associated with a third range of time delays.

A method for duty cycle error calibration, comprising:

• receiving a reference clock signal;
• comparing the reference clock signal and a feedback clock signal to detect an error;
• in response to detecting the error based on the comparing, determining whether the error is greater than a threshold;
• and
• in response to determining that the error is greater than the threshold:
• increasing a first range of time delays to a second range of time delays from which to select a time delay to delay the feedback clock signal;
• and
• delaying the feedback clock signal using the time delay to reduce the error.