Serial bus redriver with trailing edge boost circuit

A serial bus re-driver circuit, comprising:

• a serial bus terminal;
• an edge detector circuit comprising:
• an input terminal coupled to the serial bus terminal;
• and
• an output terminal;
• and
• a booster circuit coupled to the edge detector circuit, and comprising:
• a leading edge boost pulse generation circuit comprising:
• an input terminal coupled to the output terminal of the edge detector circuit;
• and
• a leading edge boost pulse output terminal;
• a trailing edge boost pulse generation circuit coupled to the leading edge boost generation circuit, and comprising:
• a pulse shortening circuit coupled to the leading edge boost pulse output terminal;
• a pulse gating circuit coupled to the pulse shortening circuit;
• and
• a drive transistor coupled to the pulse gating circuit and the serial bus terminal;
• wherein the pulse shortening circuit comprises:
• a first delay cell comprising:
• an input terminal coupled to the leading edge boost pulse output terminal;
• and
• an output terminal;
• a second delay cell comprising:
• an input terminal coupled to the output terminal of the first delay cell;
• and
• an output terminal;
• a conjunctive logic circuit comprising:
• a first input terminal coupled to the output terminal of the first delay cell;
• a second input terminal coupled to the output terminal of the second delay cell;
• and
• an output terminal coupled to the drive transistor;
• wherein:
• the pulse gating circuit is a first pulse gating circuit;
• the drive transistor is a first drive transistor;
• and
• the serial bus re-driver circuit further comprises:
• a second drive transistor;
• a third delay cell comprising:
• an input terminal coupled to the output terminal of the conjunctive logic circuit;
• and
• an output terminal;
• a second pulse gating circuit comprising:
• a first logic gate comprising:
• a first input terminal coupled to the output terminal of the edge detector circuit;
• a second input terminal coupled to the output terminal of the third delay cell;
• and
• an output terminal;
• and
• a second logic gate comprising:
• a first input terminal coupled to the output terminal of the first logic gate;
• a second input terminal coupled to the leading edge boost pulse output terminal;
• and
• an output terminal coupled to the second drive transistor.