Method for forming a timing circuit arrangements for flip-flops

An integrated circuit comprising:

• a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal, wherein the first time delay circuit further includes a first gate-conductor intersecting a first-type active region structure and a second-type active region structure in a first area;
• a second time delay circuit having a second input configured to receive the first clock signal and having a second output configured to generate a third clock signal from the first clock signal, wherein the second time delay circuit further includes a second gate-conductor intersecting a first-type active region structure and a second-type active region structure in a second area;
• wherein the first time delay circuit comprises a first gate via-connector in direct contact with the first gate-conductor atop the first-type active region structure in the first area, and at least a portion of the first gate via-connector in the first time delay circuit is atop the first-type active region structure in the first area;
• and
• wherein the second time delay circuit comprises a second gate via-connector in direct contact with the second gate-conductor atop the second-type active region structure in the second area, and at least a portion of the second gate-conductor in the second time delay circuit is atop the second-type active region structure in the second area.

An integrated circuit comprising:

• a first time delay circuit having a first input configured to receive a first clock signal and having a first output configured to generate a second clock signal from the first clock signal, wherein the first time delay circuit further includes a first gate-conductor intersecting a first-type active region structure and a second-type active region structure in a first area, wherein the first time delay circuit comprises a first gate via-connector in direct contact with the first gate -conductor atop the first-type active region structure in the first area, and wherein at least a portion of the first gate via-connector in the first time delay circuit is atop the first-type active region structure in the first area;
• a second time delay circuit having a second input configured to receive the first clock signal and having a second output configured to generate a third clock signal from the first clock signal, wherein the second time delay circuit further includes a second gate-conductor intersecting a first-type active region structure and a second-type active region structure in a second area, and wherein the second time delay circuit comprises a second gate via-connector in direct contact with the second gate-conductor atop the second-type active region structure in the second area;
• and
• a master-slave flip-flop having a master latch, a slave latch, and a transmission gate coupled between the master latch and the slave latch, and wherein the transmission gate is configured to receive the first clock signal and the second clock signal to control a transmission state of the transmission gate.