LED driver electromagnetic interference mitigation

A circuit comprising:

• one or more delay elements, each delay element of the one or more delay elements clocked via a clock signal, wherein a first delay element of the one or more delay elements is configured to receive a control signal as input, and wherein a second delay element of the one or more delay elements is configured to output a delayed control signal, the control signal comprising a first rising edge, the delayed control signal comprising a second rising edge, the second rising edge being later than the first rising edge;
• an oscillator configured to generate the clock signal, wherein the oscillator is configured to generate the clock signal in response to an enable signal;
• an exclusive or (XOR) gate configured to output the enable signal, wherein a first input of the XOR gate is coupled to the control signal, and a second input of the XOR gate is coupled to the delayed control signal, wherein the enable signal is generated by a XOR of the first and second inputs;
• and
• a selector coupled to the one or more delay elements, the selector configured to provide a code based on the outputs of the one or more delay elements.

A system comprising:

• a controller configured to generate a control signal;
• a circuit coupled to the controller, the circuit comprising:
• one or more delay elements, each delay element of the one or more delay elements clocked via a clock signal, wherein a first delay element of the one or more delay elements is configured to receive the control signal as input, and wherein a second delay element of the one or more delay elements is configured to output a delayed control signal, the control signal comprising a first rising edge, the delay control signal comprising a second rising edge, the second rising edge being later than the first rising edge;
• an oscillator configured to generate the clock signal, wherein the oscillator is configured to generate the clock signal in response to an enable signal;
• a selector coupled to the one or more delay elements, the selector configured to generate a code based on outputs of the one or more delay elements;
• a digital to analog converter (DAC) coupled to the selector, wherein the DAC is configured to generate a reference signal based, at least in part, on the code;
• a driver coupled to the circuit, the driver configured to generate a drive current based, at least in part, on the reference signal;
• and
• a light emitting diode coupled to the driver, the light emitting diode configured to generate an optical signal based on the drive current.