Snapback electrostatic discharge (ESD) circuit, system and method of forming the same

An electrostatic discharge (ESD) protection circuit comprising:

• a first well in a substrate, the first well having a first dopant type;
• a drain region of a first transistor, the drain region being in the first well, and having a second dopant type different from the first dopant type;
• a source region of the first transistor, the source region being in the first well, having the second dopant type, and being separated from the drain region in a first direction;
• a gate region of the first transistor, the gate region being over the first well and the substrate;
• a second well embedded in the first well, and adjacent to a portion of the source region, and the second well having the second dopant type, a top surface of the second well is coplanar with a top surface of the first well and a top surface of the source region;
• a tap well in the first well and having the first dopant type, and being coupled to the source region;
• a third well embedded in the first well, the third well having the second dopant type, and being adjacent to a portion of the drain region;
• and
• a first shallow trench isolation (STI) region adjacent to the drain region of the first transistor, and being in the third well;
• wherein the first well has a first depth in a second direction different from the first direction;
• and
• the second well has a second depth in the second direction, and the second depth is equal to the first depth.

A snapback electrostatic discharge (ESD) protection circuit comprising:

• a first well in a substrate, the first well having a first dopant type;
• a drain of a transistor, the drain being in the first well, and having a second dopant type different from the first dopant type;
• a source of the transistor, the source being in the first well, having the second dopant type, and being separated from the drain in a first direction;
• a gate of the transistor, the gate being over the first well and the substrate;
• a second well in the first well, and adjacent to a first portion of the drain, and the second well having the second dopant type;
• a third well embedded in the first well, the third well having the second dopant type, and being adjacent to a first portion of the source, a top surface of the third well is coplanar with a top surface of the first well and a top surface of the source;
• and
• a first shallow trench isolation (STI) region adjacent to the drain of the transistor, and being in the second well;
• wherein the first well has a first depth in a second direction different from the first direction;
• and
• the second well has a second depth in the second direction, and the second depth is equal to the first depth.