Low noise inverter-based voltage-to-time converter with common mode input tracking
AssigneeIntel Corporation
InventorsAmy Whitcombe, Somnath Kundu, Brent R. Carlton
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Abstract
A differential voltage-to-time converter (VTC) architecture and method of providing VTC signals are disclosed. The VTC includes a ramp generator that generates a ramp voltage, capacitors having a bottom plate coupled with the ramp generator to receive the ramp voltage, and inverters having inputs coupled to top plates of the capacitors to provide signals based on a sampled signal. A threshold voltage or supply voltage of the inverters tracks a minimum input signal voltage.
Claims20
A differential voltage-to-time converter (VTC) comprising:
- a ramp generator configured to generate a ramp voltage;
- a differential capacitance comprising first and second capacitors coupled with the ramp generator to receive the ramp voltage;
- and
- first and second inverters having inputs coupled to the differential capacitance to provide signals based on a sampled signal, the first inverter coupled to the first capacitor, the second inverter coupled to the second capacitor.
An electronic device, comprising:
- a differential voltage-to-time converter (VTC) comprising:
- a ramp generator configured to generate a ramp voltage;
- a differential capacitance comprising first and second capacitors having a bottom plate coupled with the ramp generator to receive the ramp voltage;
- and
- first and second inverters having inputs coupled to top plates of the first and second capacitors to provide signals based on a sampled signal, the first inverter coupled to the first capacitor, the second inverter coupled to the second capacitor, at least one of a supply voltage or a threshold voltage of the first and second inverters being adjusted based on environmental conditions;
- and
- a processor configured to receive an output signal from the VTC.
A method of converting a signal from an analog voltage to a time domain signal, the method comprising:
- sampling a differential input voltage onto capacitors with a common bottom plate voltage during a sampling period;
- setting the bottom plate voltage to a first voltage during the sampling period and discharging the capacitors with a fixed current to generate a ramp voltage that is common to a differential sampling voltage on the capacitors;
- supplying the differential sampling voltage to inverters that, when the differential sampling voltage crosses an inverter threshold voltage, trigger a transition of the inverters to switch output clocks from low to high;
- and
- holding the ramp voltage at a reset voltage until a next sampling period.
Dependencies are inferred from the claim text.