Data retention circuit and method

An integrated circuit (IC) comprising:

• a first power node configured to have a first voltage level;
• a second power node configured to have a second voltage level different from the first voltage level;
• a reference node configured to have a reference voltage level;
• first and second n-wells;
• a master latch configured to output a first data bit based on a received data bit;
• a slave latch configured to output a second data bit based on the first data bit and an output data bit based on a selected one of the first data bit or a third data bit;
• a first level shifter configured to output the third data bit based on a complementary bit pair;
• and
• a retention latch comprising a second level shifter and a pair of inverters configured to output the complementary bit pair based on the second data bit, wherein
• each of the slave latch and the first level shifter is coupled to each of the first power node, the reference node, and the first n-well, and
• the retention latch is coupled to each of the second power node, the reference node, and the second n-well.

A method of retaining a data bit, the method comprising:

• based on a received data bit, outputting a first data bit from a master latch;
• outputting, from a slave latch, a second data bit based on the first data bit and an output data bit based on a selected one of the first data bit or a third data bit;
• outputting, from a first level shifter, the third data bit based on a complementary bit pair;
• and
• based on the second data bit, outputting the complementary bit pair from a second level shifter and pair of inverters of a retention latch,
• wherein
• each of the slave latch and the first level shifter is coupled between a reference node and a first power node capable of having a first voltage level, and
• the retention latch is coupled between the reference node and a second power node capable of having a second voltage level different from the first voltage level.