Delayed cache writeback instructions for improved data sharing in manycore processors
AssigneeIntel Corporation
InventorsWim Heirman, Stijn Eyerman, Ibrahim Hur
Life of this patent
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Abstract
Methods and apparatus relating to one or more delayed cache writeback instructions for improved data sharing in manycore processors are described. In an embodiment, a delayed cache writeback instruction causes a cache block in a modified state in a Level 1 (L1) cache of a first core of a plurality of cores of a multi-core processor to a Modified write back (M.wb) state. The M.wb state causes the cache block to be written back to LLC upon eviction of the cache block from the L1 cache. Other embodiments are also disclosed and claimed.
Claims14
An apparatus comprising:
- a Last Level Cache (LLC) coupled to a plurality of cores of a multi-core processor, the LLC to store data accessible by the plurality of the cores;
- decoder circuitry to decode an instance of a single instruction, the instance of the single instruction to include a field to indicate a location that is to store a cache block address and an opcode to indicate that execution circuitry is to cause a state of a cache block at the cache block address to be changed to a modified writeback state, wherein the cache block in the modified writeback state is to indicate that the cache block is stored to both the LLC and a Level 2 (L2) cache upon eviction of the cache block from a Level 1 (L1) cache;
- and
- execution circuitry to execute the decoded instance of the single instruction according to the opcode.
One or more non-transitory computer-readable media comprising one or more instructions that when executed on at least one processor configure the at least one processor to perform one or more operations to:
- decode an instance of a single instruction, the instance of the single instruction to include a field to indicate a location that is to store a cache block address and an opcode to indicate that execution circuitry is to cause a state of a cache block at the cache block address to be changed to a modified writeback state, wherein the cache block in the modified writeback state is to indicate that the cache block is stored to both a Last Level Cache (LLC) and a Level 2 (L2) cache upon eviction of the cache block from a Level 1 (L1) cache;
- and
- execute the decoded instance of the single instruction according to the opcode.
Dependencies are inferred from the claim text.