Current-balance control
AssigneeIntel Corporation
InventorsChristopher Schaef, Juan Munoz Constantine, Alexander Lyakhov
Life of this patent
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Abstract
Embodiments herein relate to identifying, by phase current balancing (PCB) circuitry, an indication of whether a measured current of a pulse-width modulated (PWM) signal of a plurality of PWM signals is greater than or less than an average current of the plurality of PWM signals. Embodiments further relate to adjusting, by the PCB circuitry, a bias-value of a non-modulated edge of a duty cycle of the PWM signal. Other embodiments may be described and claimed.
Claims17
One or more non-transitory computer-readable media comprising instructions that, upon execution of the instructions by one or more processor of an electronic device, are to cause the electronic device to:
- set a bias-value of a non-modulated edge of a duty cycle of a pulse-width modulated (PWM) signal of a plurality of PWM signals to a value greater than 0;
- determine a current of the PWM signal;
- identify, based on the current of the PWM signal and an average current of the plurality of PWM signals, an adjustment to be made to the duty cycle;
- adjust, based on the adjustment, the bias-value of a non-modulated edge of the duty cycle;
- and
- adjust, based on a delay-lock loop (DLL) bias current, the non-modulated edge of the duty cycle.
Phase current balancing (PCB) circuitry comprising:
- a current comparator to:
- determine a current of a pulse-width modulated (PWM) signal of a plurality of PWM signals;
- determine an average current of the plurality of PWM signals;
- and
- output an indication of whether the current of the PWM signal is greater than or less than the average current of the plurality of PWM signals;
- and
- PCB logic communicatively coupled with the current comparator, the PCB logic to:
- identify, based on the indication, an adjustment to be made to a duty cycle;
- and
- output, based on the adjustment, a bias control signal to cause an adjustment to a bias-value of a non-modulated edge of a duty cycle of the PWM signal, wherein the PCB circuitry is to adjust the non-modulated edge of the duty cycle based on a delay-lock loop (DLL) bias current.
A method comprising:
- identifying, by phase current balancing (PCB) circuitry, an indication of whether a measured current of a pulse-width modulated (PWM) signal of a plurality of PWM signals is greater than or less than an average current of the plurality of PWM signals;
- and
- adjusting, by the PCB circuitry, a bias-value of a non-modulated edge of a duty cycle of the PWM signal, wherein adjusting the bias-value of the non-modulated edge of the duty cycle is based on a delay-lock loop (DLL) bias current.
Dependencies are inferred from the claim text.