Far memory allocator for data center stranded memory

An integrated circuit device, comprising:

• a memory to store a local translation table;
• a first interface, for communication and to access local memory using local memory addresses;
• a second interface, for communication with other far memory allocators, using fabric addresses;
• and
• a processing circuit, operatively coupled to the memory, the first interface, and the second interface, the processing circuit to:
• as a donor determine availability and allocate, on a dynamic basis, portions of the local memory, each as first far memory, to the other far memory allocators, and each with corresponding first mapping of first local addresses and first fabric addresses in the local translation table;
• as a requester receive one or more allocations of portions of further local memory, each as second far memory, from the other far memory allocators, and each with corresponding second mapping of second local addresses and second fabric addresses in the local translation table;
• generate a priority list comprising a plurality of node identifiers associated with a plurality of nodes and a plurality of memory availability indicators, for identifying far memory available for allocation from other servers;
• determine, based on the priority list, that a first node of the plurality of nodes is associated with a lowest latency with respect to other nodes in the plurality of nodes;
• and
• query the first node, from the priority list, for a fabric address to use to access a far memory allocation.