Circuits and methods for debouncing signals produced by a rotary encoder

A circuit, comprising:

• a first input node configured to receive a first input signal;
• a second input node configured to receive a second input signal;
• wherein said first input signal and said second input signal are in quadrature phase;
• an edge detector circuit configured to receive said first input signal and produce a pulsed signal indicative of edges detected in said first input signal;
• a pulse skip and reset circuit configured to receive said pulsed signal and said second input signal, and produce a reset signal indicative of pulses detected in said pulsed signal while said second input signal is de-asserted;
• and
• a sampling circuit configured to generate an output signal that is de-asserted in response to assertion of said second input signal and is asserted in response to a pulse of said reset signal;
• wherein said edge detector circuit comprises:
• a delay circuit configured to produce a delayed replica of said first input signal;
• and
• a logic circuit configured to apply one of exclusive-NOR signal processing or exclusive-OR signal processing to said first input signal and said delayed replica of said first input signal to produce said pulsed signal.

A circuit, comprising:

• a first input node configured to receive a first input signal;
• a second input node configured to receive a second input signal;
• wherein said first input signal and said second input signal are in quadrature phase;
• an edge detector circuit configured to receive said first input signal and produce a pulsed signal indicative of edges detected in said first input signal;
• a pulse skip and reset circuit configured to receive said pulsed signal and said second input signal, and produce a reset signal indicative of pulses detected in said pulsed signal while said second input signal is de-asserted;
• and
• a sampling circuit configured to generate an output signal that is de-asserted in response to assertion of said second input signal and is asserted in response to a pulse of said reset signal;
• wherein said pulse skip and reset circuit comprises a logic circuit configured to apply one of NOR signal processing or OR signal processing to said pulsed signal and said second input signal to produce said reset signal.

A circuit, comprising:

• a first input node configured to receive a first input signal;
• a second input node configured to receive a second input signal;
• wherein said first input signal and said second input signal are in quadrature phase;
• an edge detector circuit configured to receive said first input signal and produce a pulsed signal indicative of edges detected in said first input signal;
• a pulse skip and reset circuit configured to receive said pulsed signal and said second input signal, and produce a reset signal indicative of pulses detected in said pulsed signal while said second input signal is de-asserted;
• and
• a sampling circuit configured to generate an output signal that is de-asserted in response to assertion of said second input signal and is asserted in response to a pulse of said reset signal;
• wherein said sampling circuit comprises a flip-flop having a clock input terminal configured to receive said second input signal, a clear input terminal configured to receive said reset signal, a data input terminal configured to receive a data input signal having a fixed logic value, at a preset input terminal configured to receive a preset input signal having a fixed logic value, and a data output terminal configured to produce said output signal.

A circuit, comprising:

• an input configured to receive first and second periodic digital signals in phase quadrature having a frequency indicative of speed of mechanical rotation and phase relationship indicative of direction of mechanical rotation;
• an edge detector circuit configured to detect edges of the first periodic digital signal and produce a signal pulse for each detected edge;
• a pulse skip and reset circuit configured to generate a reset signal which includes only those signal pulses output from the edge detector circuit which occur when the second periodic digital signal is de-asserted;
• and
• a set/reset circuit having a set input configured to receive the second periodic digital signal and set an output signal to a first logic state in response thereto, and a reset input configured to receive the reset signal and reset the output signal to a second logic state in response thereto.

A method, comprising:

• receiving a first input signal;
• receiving a second input signal;
• wherein said first input signal and said second input signal are in quadrature phase;
• producing a pulsed signal including a pulse for each edge detected in said first input signal;
• producing a reset signal which includes only those pulses in said pulsed signal which occur when said second input signal is de-asserted;
• and
• producing an output signal that is de-asserted in response to assertion of said second input signal and is asserted in response to a pulse being detected in said reset signal.