Automatic clock rate synchronization for 1-wire radio frequency front-end interface
AssigneeQUALCOMM Incorporated
InventorsLalan Jee Mishra, Umesh Srikantiah, Richard Dominic Wietfeldt
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AssigneeQUALCOMM Incorporated
InventorsLalan Jee Mishra, Umesh Srikantiah, Richard Dominic Wietfeldt
Estimating the term…
A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.
A clock generation circuit, comprising:
An apparatus comprising:
A method for generating a rate matched clock signal, comprising:
Dependencies are inferred from the claim text.