Method of manufacturing integrated circuit

A method of manufacturing an integrated circuit comprising:

• calibrating an optical proximity correction (OPC) model by adjusting a first parameter and a second parameter, the first parameter including an effect caused by an electron-beam lithography tool for making a photomask, and the second parameter including one or more of a geometric feature of a structure and a manufacturing process to make the structure;
• calculating a grid pattern density map of a device layout;
• performing an OPC to generate an optimized mask layout from at least the grid pattern density map and the calibrated OPC model;
• manufacturing a photomask from at least the optimized mask layout;
• and
• manufacturing the integrated circuit by a process comprising photolithography employing the photomask.

A method of manufacturing an integrated circuit comprising:

• retrieving a parameter comprising an effect caused by an electron-beam lithography tool for making a photomask;
• calibrating an optical proximity correction (OPC) model from at least the parameter;
• calculating a grid pattern density map of a device layout;
• generating a correction map from at least the grid pattern density map of the device layout and the parameter;
• performing an OPC to generate an optimized mask layout from at least the generated correction map and the calibrated OPC model;
• manufacturing a photomask from at least the optimized mask layout;
• and
• manufacturing the integrated circuit by a process comprising photolithography employing the photomask.