FinFET thyristors with embedded transistor control for protecting high-speed communication systems

A fin field-effect transistor (FinFET) thyristor protection circuit comprising:

• a thyristor comprising a PNP bipolar transistor and an NPN bipolar transistor, wherein the PNP bipolar transistor includes an emitter connected to a signal terminal and formed from a first plurality of p-type active (P+) regions extending in a first direction in an n-type well (NW), a base formed from the NW, and a collector formed from a p-type well (PW), and wherein the NPN bipolar transistor includes an emitter connected to a ground terminal and formed from a first plurality of n-type active (N+) regions extending in the first direction in the PW, a base formed from the PW, and a collector formed from the NW;
• and
• FinFET triggering circuitry comprising a first cascoded p-type FinFET and a second cascoded p-type FinFET connected in series and configured to trigger activation of the thyristor in response to an electrical overstress event received between the signal terminal and the ground terminal, wherein a source and a gate of the first cascoded p-type FinFET are connected to the signal terminal, and wherein a drain of the second cascoded p-type FinFET is formed in the NW and connected to the base of the NPN bipolar transistor by a direct metal connection in a second direction substantially perpendicular to the first direction, and wherein the first cascoded p-type FinFET and the second cascoded p-type FinFET are configured to activate to provide a trigger current from the signal terminal in response to the electrical overstress event received between the signal terminal and the ground terminal, the trigger current flowing in the second direction via the direct metal connection to the base of the NPN bipolar transistor.

A method of protecting an interface of a communication system, the method comprising:

• receiving an electrical overstress event between a signal terminal and a ground terminal;
• providing a first current path from the signal terminal to the ground terminal through FinFET triggering circuitry in response to the electrical overstress event, the FinFET triggering circuitry comprising a first cascoded p-type FinFET and a second cascoded p-type FinFET connected in series, wherein a source and a gate of first cascoded p-type FinFET are connected to the signal terminal, and wherein a drain of the second cascoded p-type FinFET is formed in an n-type well (NW);
• and
• triggering activation of a thyristor using the FinFET triggering circuitry, wherein the thyristor comprises a PNP bipolar transistor and an NPN bipolar transistor, wherein the PNP bipolar transistor includes an emitter connected to the signal terminal and formed from a first plurality of p-type active (P+) regions extending in a first direction in the NW, a base formed from the NW, and a collector formed from a p-type well (PW), and wherein the NPN bipolar transistor includes an emitter connected to the ground terminal and formed from a first plurality of n-type active (N+) regions extending in the first direction in the PW, a base formed from the PW and connected to the drain of the second cascoded p-type FinFET by a direct metal connection in a second direction substantially perpendicular to the first direction, and a collector formed from the NW, and wherein triggering activation of the FinFET triggering circuitry includes the first cascoded p-type FinFET and the second cascoded p-type FinFET providing a trigger current from the signal terminal in response to the electrical overstress event received between the signal terminal and the ground terminal, the trigger current flowing in the second direction via the direct metal connection to the base of the NPN bipolar transistor.