Amplitude optimized reflection canceller in parallel channel equalizers

An equalizer for equalizing a digital signal, comprising:

• a plurality of delays;
• a plurality of multiplexers;
• and
• one or more adders,
• wherein the equalizer is configured to:
• receive, at the plurality of delays or at the plurality of multiplexers, a plurality of samples of the signal in a plurality of unit intervals (UIs) of a channel response of the digital signal, the plurality samples comprising a first plurality of samples of a primary response and a second plurality of samples of one or more reflection responses;
• equalize, at the plurality of delays and the plurality of multiplexers, the first plurality of samples using a first set bitwidth;
• equalize, at the plurality of delays and the plurality of multiplexers, the second plurality of samples using one or more further bitwidths, wherein the first set bitwidth is greater than each of the one or more further bitwidths;
• and
• generate, at the one or more adders, an equalized digital signal.