Integrated circuit package having wirebonded multi-die stack

An integrated circuit (IC) assembly comprising:

• a semiconductor package, comprising:
• a first integrated circuit having an active side and a backside opposite the active side, the active side having a plurality of die level interconnects thereon;
• a redistribution layer, the redistribution layer coupled to the active side of the first integrated circuit, and the redistribution layer coupled to a plurality of package level interconnects;
• a first via bar laterally adjacent to and distanced apart from a first edge of the first integrated circuit, the first via bar coupled to the redistribution layer, and the first via bar extending above the backside of the first integrated circuit;
• a second via bar laterally adjacent to and distanced apart from a second edge of the first integrated circuit opposite the first edge of the first integrated circuit, the second via bar coupled to the redistribution layer, and the second via bar extending above the backside of the first integrated circuit;
• a first encapsulation layer laterally surrounding and in contact with the first integrated circuit;
• an electrically insulative material in direct physical contact with the first encapsulation layer, and the electrically insulative material having an uppermost surface above a level of the backside of the first integrated circuit, wherein the first via bar and the second via bar are within and in contact with the electrically insulative material;
• a second integrated circuit above the first integrated circuit, the second integrated circuit having an active side and a backside opposite the active side, the active side of the second integrated circuit having a plurality of integrated circuit level interconnects thereon, the backside of the second integrated circuit facing the backside of the first integrated circuit;
• a third integrated circuit above the second integrated circuit, the third integrated circuit having an active side and a backside opposite the active side, the active side of the third integrated circuit having a plurality of integrated circuit level interconnects thereon, the backside of the third integrated circuit facing the active side of the second integrated circuit;
• a first wire bond electrically connecting one of the plurality of integrated circuit level interconnects of the second integrated circuit to the first via bar;
• a second wire bond electrically connecting one of the plurality of integrated circuit level interconnects of the third integrated circuit to the second via bar;
• and
• a second encapsulation layer laterally adjacent the second integrated circuit, the third integrated circuit, the first wire bond, and the second wire bond, wherein the second encapsulation layer is further over the active side of the third integrated circuit;
• and
• a circuit board having a plurality of electrical routing features disposed therein and a plurality of pads disposed thereon, wherein the plurality of pads are electrically coupled with the plurality of package level interconnects.