Hierarchical statisically multiplexed counters and a method thereof
AssigneeMarvell Asia Pte Ltd
InventorsWeihuang Wang, Gerald Schmidt, Srinath Atluri, Weinan Ma, Shrikant Sundaram Lnu
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Abstract
Embodiments of the present invention relate to an architecture that uses hierarchical statistically multiplexed counters to extend counter life by orders of magnitude. Each level includes statistically multiplexed counters. The statistically multiplexed counters includes P base counters and S subcounters, wherein the S subcounters are dynamically concatenated with the P base counters. When a row overflow in a level occurs, counters in a next level above are used to extend counter life. The hierarchical statistically multiplexed counters can be used with an overflow FIFO to further extend counter life.
Claims20
A counter architecture implemented in a network device, the counter architecture comprising:
- a mirrored shift logic;
- and
- a hierarchy of levels of statistically multiplexed counters, wherein each level of the hierarchy of levels includes N counters arranged in rows having P base counters, and further wherein the mirrored shift logic extends the P base counters to a full width such that a full range of shifting is reduced.
A non-transitory computer-readable medium storing a mirrored shift logic and a hierarchy of levels of statistically multiplexed counters, wherein each level of the hierarchy of levels includes N counters arranged in rows having P base counters, and further wherein the mirrored shift logic extends the P base counters to a full width such that a full range of shifting is reduced.
Dependencies are inferred from the claim text.