Organic light emitting diode display

An organic light emitting diode display comprising:

• a substrate which includes a display area and a non-display area;
• an organic light emitting diode disposed in the display area;
• a plurality of transistors connected to the organic light emitting diode and disposed in the display area;
• and
• a gate driver disposed in the non-display area,
• wherein the gate driver includes:
• a clock wiring circuit which includes a first signal line and a second signal line extending in a first direction, respectively;
• a resistance adjusting circuit which includes a first resistance line electrically connected to the first signal line and a second resistance line electrically connected to the second signal line;
• and
• a gate driving circuit connected to the resistance adjusting circuit and which includes a plurality of stages for applying a gate signal,
• wherein the second signal line is disposed closer to the gate driving circuit than the first signal line,
• each of the first resistance line and the second resistance line includes a winding concave-convex portion,
• the plurality of stages are arranged in the first direction,
• a length of the concave-convex portion of the first resistance line in a second direction perpendicular to the first direction is shorter than a length of the concave-convex portion of the second resistance line in the second direction,
• the second resistance line includes another portion between the concave-convex portion thereof and a stage of the plurality of stages,
• the another portion of the second resistance line is disposed in a different conductive layer from the concave-convex portion of the second resistance line and is electrically connected to the concave-convex portion of the second resistance line through a contact hole, and
• the concave-convex portion of the second resistance line does not overlap an end of the another portion directly connected to the stage in the second direction in a plan view.

An organic light emitting diode display comprising:

• a substrate which includes a display area and a non-display area;
• a first lower resistance line and a second lower resistance line disposed in the non-display area;
• an insulating layer disposed on the first lower resistance line and the second lower resistance line;
• an upper resistance line disposed on the insulating layer;
• and
• an interlayer insulating layer disposed on a portion of the upper resistance line,
• wherein the upper resistance line includes a first upper resistance line disposed on a top surface of the interlayer insulating layer and a second upper resistance line disposed under a bottom surface of the interlayer insulating layer,
• the first lower resistance line is electrically connected to the first upper resistance line and has higher resistivity than the first upper resistance line, and the second lower resistance line is electrically connected to the second upper resistance line and has higher resistivity than the second upper resistance line, and
• the first lower resistance line is electrically connected to the first upper resistance line through an opening defined in the insulating layer and the interlayer insulating layer.