Array substrate and display apparatus

An array substrate, comprising a plurality of pixel driving circuits, a plurality of light emitting elements respectively connected to the plurality of pixel driving circuits, a node connecting line in the first signal line layer, and an auxiliary capacitor electrode;

• wherein a respective pixel driving circuit comprises a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor;
• an active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer;
• the active layer of the driving transistor comprises a first semiconductor material;
• and
• the active layer of the transistor comprises a second semiconductor material different from the first semiconductor material;
• wherein the node connecting line connects the first electrode of the transistor to the first capacitor electrode, which functions as a gate electrode of the driving transistor;
• wherein the node connecting line is connected to the auxiliary capacitor electrode through a fifth via extending through at least a passivation layer;
• and
• wherein the array substrate further comprises an auxiliary capacitor comprising the auxiliary capacitor electrode and a portion of a respective first gate line of a plurality of first gate lines, the respective first gate line being connected to a gate electrode of a first transistor and a gate electrode of a second transistor.

An array substrate, comprising a plurality of pixel driving circuits, a plurality of light emitting elements respectively connected to the plurality of pixel driving circuits, and a node connecting line in a first signal line layer;

• wherein a respective pixel driving circuit comprises a driving transistor, a storage capacitor, and a transistor having a gate electrode connected to a respective second gate line of a plurality of second gate lines, a first electrode connected to a first capacitor electrode of the storage capacitor, and a second electrode connected to a second electrode of a first reset transistor, the transistor being configured to receive a reset signal through the first reset transistor;
• an active layer of the driving transistor and an active layer of the transistor are spaced apart from each other by at least an insulating layer;
• the active layer of the driving transistor comprises a first semiconductor material;
• and
• the active layer of the transistor comprises a second semiconductor material different from the first semiconductor material;
• wherein the respective second gate line comprises a first branch and a second branch respectively in two different layers;
• the first branch is in a same layer as a second capacitor electrode of the storage capacitor;
• the second branch is in a same layer as a plurality of first reset signal lines, a respective first reset signal line of the plurality of first reset signal lines is configured to provide a reset signal to the first electrode of the transistor;
• and
• the node connecting line crosses over the first branch and the second branch in a present stage.