Array substrate, method for manufacturing the same, display panel and display device

A method for manufacturing an array substrate, wherein the array substrate comprises a driving circuitry structure, and the driving circuitry structure comprises at least one transparent conductive layer for forming a transparent line, and an active layer and a plurality of metal layers for forming a plurality of pixel driving circuitries, the array substrate comprises a display region, and the display region comprises an opening region,

• wherein the method comprises:
• providing a base substrate;
• patterning a transparent conductive material layer and an active material layer on the base substrate through a same mask to form the transparent conductive layer and the active layer laminated one on another and in contact with each other, and/or patterning the transparent conductive material layer and a metal material layer on the base substrate through a same mask to form the transparent conductive layer and the metal layer laminated one on another and in contact with each other;
• and
• forming an anode material layer at a side of the driving circuitry structure away from the base substrate, and patterning the anode material layer to obtain a plurality of anodes, each anode at the opening region being electrically coupled to a corresponding pixel driving circuitry via the transparent line;
• wherein the plurality of metal layers comprises a first gate metal layer arranged at a side of the active layer away from the base substrate, a second gate metal layer arranged at a side of the first gate metal layer away from the active layer, a first source/drain metal layer arranged at a side of the second gate metal layer away from the first gate metal layer, and a second source/drain metal layer arranged at a side of the first source/drain metal layer away from the second gate metal layer;
• and
• the driving circuitry structure further comprises a first insulation layer arranged between the active layer and the first gate metal layer, a second insulation layer arranged between the first gate metal layer and the second gate metal layer, a third insulation layer arranged between the second gate metal layer and the first source/drain metal layer, a fourth insulation layer arranged between the first source/drain metal layer and the second source/drain metal layer, and a fifth insulation layer arranged between the second source/drain metal layer and the anode layer.