A nonvolatile semiconductor memory device comprising:
- a plurality of first wiring layers extended in a first direction and arranged in a second direction crossing the first direction;
- a plurality of second wiring layers extended in the second direction and arranged in the first direction above the plurality of the first wiring layers;
- a plurality of third wiring layers extended in the first direction and arranged in the second direction above the plurality of the second wiring layers;
- a first memory cell disposed between one second wiring layer of the plurality of the second wiring layers and one first wiring layer of the plurality of the first wiring layers at a crossing portion between the plurality of the second wiring layers and the plurality of the first wiring layers, the first memory cell comprising a first cell unit including a first variable resistance film and a first selector unit including a first selector;
- a second memory cell disposed between one third wiring layer of the plurality of the third wiring layers and the one second wiring layer at a crossing portion between the plurality of the third wiring layers and the plurality of the second wiring layers, the second memory cell comprising a second cell unit including a second variable resistance film and a second selector unit including a second selector;
- a third memory cell disposed between the one first wiring layer and another closest second wiring layer adjacent in the first direction to the second wiring layer on which the first memory cell is disposed, the third memory cell comprising a third cell unit including a third variable resistance film and a third selector unit including a third selector;
- and
- an insulation layer disposed between the first memory cell and the third memory cell, wherein
- the second wiring layer has a stacked structure including at least two layers having mutually different materials, wherein
- the second wiring layer includes a second lower wiring layer and a second upper wiring layer, one side of the second lower wiring layer is connected to the first memory cell, the other side of second lower wiring layer is connected to the second upper wiring layer, one side of the second upper wiring layer is connected to the second lower wiring layer, and the other side of the second upper wiring layer is connected to the second memory cell, wherein
- a part of the one side of second upper wiring layer is connected to the second lower wiring layer, and a rest of the one side of second upper wiring layer is not connected to the second lower wiring layer but is connected to the insulation layer disposed between the first memory cell and the third memory cell.