SONOS memory cell structure and fabricating method of the same

A fabricating method of a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell structure, comprising:

• providing a silicon substrate, wherein the silicon substrate is divided into a memory unit region, an input output region and a high voltage transistor region;
• forming a tunnel silicon oxide layer and a silicon nitride layer covering the memory unit region;
• forming a first silicon oxide layer covering and contacting the silicon nitride layer, the input output region and the high voltage transistor region;
• removing the first silicon oxide layer within the input output region entirely and removing part of the first silicon oxide layer within the memory unit region to segment the first silicon oxide layer within the memory unit region into two third silicon oxide layers;
• forming two second silicon oxide layers, wherein one of the two second silicon oxide layers is between the two third silicon oxide layers and another one of the two second silicon oxide layers is within the input output region;
• and
• forming a control gate covering the one of the two second silicon oxide layers within the memory unit region and covering the two third silicon oxide layers, forming a high voltage gate covering the first silicon oxide layer within the high voltage transistor region, and forming a transistor gate covering the another one of the two second silicon oxide layers within the input output region.