United states 3D memory semiconductor devices and structures with memory cells

A 3D memory device, the device comprising:

• a first structure comprising a plurality of memory cells,
• wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
• wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
• a plurality of memory-line pillars,
• wherein said plurality of memory-line pillars are vertically oriented, and
• wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step;
• and
• a control level comprising a memory controller circuit,
• wherein said memory controller circuit comprises plurality of a row buffers,
• wherein said memory controller circuit comprises a configuration to perform a self-differential read cycle,
• wherein said control level is bonded to said first structure, and
• wherein said bonded comprises hybrid bonding.

A 3D memory device, the device comprising:

• a first structure comprising a plurality of memory cells,
• wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
• wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
• a plurality of memory-line pillars,
• wherein said plurality of memory-line pillars are vertically oriented, and
• wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step;
• and
• a control level comprising a memory controller circuit,
• wherein said channel comprises recrystallized polysilicon,
• wherein said memory controller circuit comprises a configuration to perform a self-differential read cycle,
• wherein said control level is bonded to said first structure, and
• wherein said bonded comprises hybrid bonding.

A 3D memory device, the device comprising:

• a first structure comprising a plurality of memory cells,
• wherein each memory cell of said plurality of memory cells comprises at least one memory transistor,
• wherein each of said at least one memory transistor comprises a source, a drain, and a channel;
• a plurality of memory-line pillars,
• wherein said plurality of memory-line pillars are vertically oriented, and
• wherein said at least one memory transistor is self-aligned to an overlaying another said at least one memory transistor, both being processed following a same lithography step;
• and
• a control level comprising a memory controller circuit,
• wherein said memory controller circuit comprises plurality of a row buffers,
• wherein said memory controller circuit comprises a calibration mode control circuit,
• wherein said control level is bonded to said first structure, and
• wherein said bonded comprises hybrid bonding.