Semiconductor devices and manufacturing methods of the same

A semiconductor device, comprising:

• a substrate arranged primarily in a horizontal direction, in a cross-sectional view, having a first region and a second region following the first region in the horizontal direction;
• a plurality of gate conductive regions spaced apart from each other and stacked in a vertical direction perpendicular to the horizontal direction, the plurality of gate conductive regions including a first gate conductive region and a plurality of second gate conductive regions;
• a plurality of gate insulating regions, each surrounded in the horizontal direction by each of the plurality of second gate conductive regions, each of the plurality of gate conductive regions being disposed within a horizontal plane of a single corresponding gate insulating region of the plurality of gate insulating regions;
• a plurality of channels disposed in the first region of the substrate, passing through the plurality of gate conductive regions, and each including a channel region having an annular form;
• and
• a contact plug disposed in the second region of the substrate, filling a contact hole passing through the first gate conductive region and the plurality of gate insulating regions, and electrically connected to the first gate conductive region,
• wherein a side surface of the contact plug has protruding portions protruding outwardly in the horizontal direction toward the plurality of second gate conductive regions, and
• wherein the semiconductor device further comprises:
• a first dielectric layer horizontally extended along the first gate conductive region and covering an upper surface and a lower surface of the first gate conductive region;
• and
• a plurality of second dielectric layers horizontally extended along the plurality of second gate conductive regions and covering upper surfaces and lower surfaces of the plurality of second gate conductive regions.

A semiconductor device, comprising:

• a substrate having a first region and a second region;
• a plurality of gate conductive regions spaced apart from each other and stacked in a direction perpendicular to an upper surface of the substrate, the plurality of gate conductive regions including a first gate conductive region and a plurality of second gate conductive regions;
• a plurality of gate insulating regions, each surrounded at least partially by each of the plurality of second gate conductive regions;
• a plurality of channels disposed in the first region of the substrate, passing through the plurality of gate conductive regions, and each including a channel region having an annular form;
• a contact plug disposed in the second region of the substrate, filling a contact hole passing through the first gate conductive region and the plurality of gate insulating regions, and electrically connected to the first gate conductive region;
• a first dielectric layer horizontally extended along the first gate conductive region and covering an upper surface and a lower surface of the first gate conductive region;
• and
• a plurality of second dielectric layers horizontally extended along the plurality of second gate conductive regions and covering upper surfaces and lower surfaces of the plurality of second gate conductive regions,
• wherein the plurality of second dielectric layers cover side surfaces of the plurality of second gate conductive regions facing the contact plug, and the first dielectric layer exposes a side surface of the first gate conductive region facing the contact plug.