Semiconductor storage device

A semiconductor storage device provided with a read only memory (ROM) cell, comprising:

• a word line extending in a first direction parallel to a substrate plane;
• first and second bit lines extending in a second direction parallel to the substrate plane and perpendicular to the first direction;
• and
• a ground power supply line extending in the second direction, wherein:
• the ROM cell includes:
• a first nanowire field effect transistor (FET) provided between the first bit line and the ground power supply line, a second nanowire FET provided between the second bit line and the ground power supply line, formed above the first nanowire FET, nanowires as channel portions of the first and second nanowire FET extending in the second direction and overlapping each other as viewed in plan, a first local interconnect connected to a source of the first nanowire FET and connected to the first bit line or the ground power supply line, a second local interconnect connected to a drain of the first nanowire FET and connected to the first bit line or the ground power supply line, a third local interconnect connected to a source of the second nanowire FET and connected to the second bit line or the ground power supply line, and a fourth local interconnect connected to a drain of the second nanowire FET and connected to the second bit line or the ground power supply line, gates of the first and second nanowire FETs are connected to the word line, and first data is stored in the ROM cell depending on whether the first and second local interconnects are connected to a same line, or different lines, out of the first bit line and the ground power supply line, and second data is stored in the ROM cell depending on whether the third and fourth local interconnects are connected to a same line, or different lines, out of the second bit line and the ground power supply line;
• and
• wherein the first, second, third and fourth local interconnects extend in the first direction, the first and third local interconnects overlap each other as viewed in plan, and the second and fourth local interconnects overlap each other as viewed in plan.