Memory device having error detection function, semiconductor device, and electronic device

A memory device comprising:

• a plurality of first element layers;
• a second element layer comprising an error detection circuit;
• a semiconductor substrate comprising a driver circuit;
• and
• a sense amplifier and a precharge circuit,
• wherein the second element layer is positioned between the semiconductor substrate and the plurality of first element layers,
• wherein the plurality of first element layers each comprise a memory cell,
• wherein the plurality of first element layers are stacked over each other,
• wherein the memory cell comprises a first transistor,
• wherein the error detection circuit comprises a second transistor,
• wherein the driver circuit comprises a third transistor,
• wherein the sense amplifier comprises a fourth transistor,
• wherein the precharge circuit comprises a fifth transistor,
• wherein the first transistor and the second transistor each comprise a metal oxide in a channel formation region,
• wherein the third transistor comprises silicon in a channel formation region,
• wherein the first transistor and the second transistor each comprise a front gate and a back gate, and
• wherein a bit line provided in a direction perpendicular to the semiconductor substrate is electrically connected to the fourth transistor and the fifth transistor via a sixth transistor.

A memory device comprising:

• first to N-th first element layers;
• a second element layer comprising a switch circuit;
• and
• a semiconductor substrate,
• wherein a K-th first element layer of the first to N-th first element layers comprises a memory cell using a first transistor formed in the K-th first element layer,
• wherein the second element layer comprises an error detection circuit using a second transistor formed in the second element layer,
• wherein the semiconductor substrate comprises a driver circuit using a third transistor formed in the semiconductor substrate,
• wherein the second element layer is stacked over the semiconductor substrate,
• wherein the K-th first element layer of the first to N-th first-element layers is stacked over the second element layer,
• wherein the K-th first element layer of the first to N-th first element layers is stacked over the (K−1)-th first element layer,
• wherein N is a natural number greater than or equal to 2,
• wherein K is an integer greater than or equal to 2 and less than or equal to N,
• wherein the first transistor and the second transistor each comprise a metal oxide in a channel formation region,
• wherein the first transistor and the second transistor each comprise a front gate and a back gate,
• wherein the third transistor comprises silicon in a channel formation region,
• wherein the switch circuit comprises a first switch and a second switch,
• wherein the first switch of the switch circuit is electrically connected to a bit line via a fourth transistor, and
• wherein the second switch of the switch circuit is electrically connected to the error detection circuit.