Methods of manufacturing a semiconductor device using a mask

A method of manufacturing a semiconductor device, the method comprising:

• forming a first sacrificial layer and a first active layer on a substrate;
• forming a first mask pattern on a portion of the substrate;
• etching the first sacrificial layer and the first active layer partially using the first mask pattern as a mask to expose a portion of a top surface of the substrate;
• forming a first semiconductor layer and a second semiconductor layer on the exposed portion of the top surface of the substrate;
• forming staked sacrificial layers and active layers on the first active layer and the semiconductor layer, the active layers including an uppermost second active layer;
• forming a second mask pattern on a portion of the uppermost second active layer;
• forming a trench using the second mask pattern as an etch mask, the trench defining a first active pattern and a second active pattern;
• and
• removing the sacrificial layers to form a first channel pattern and a second channel pattern on the first active pattern and the second active pattern, respectively,
• wherein a top surface of the first semiconductor layer and a top surface of the second semiconductor layer are coplanar with a top surface of the first active layer,
• wherein the first semiconductor layer is a portion of the first active pattern, and
• wherein the second semiconductor layer is a portion of the second active pattern.

A method of manufacturing a semiconductor device, the method comprising:

• forming a first active pattern and a second active pattern on a substrate;
• forming a sacrificial pattern extending in a first direction on the first active pattern and the second active pattern, the first direction extending in parallel with an upper surface of the substrate;
• etching the first active pattern and the second active pattern using the sacrificial pattern as a mask to form a first recess in the first active pattern and a second recess in the second active pattern, the first active pattern and the second active pattern respectively including semiconductor patterns exposed by the first recess and the second recess;
• forming a first source/drain pattern in the first recess and a second source/drain pattern in the second recess;
• removing the sacrificial pattern to expose a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern;
• and
• sequentially forming a gate insulating layer and a gate electrode on the exposed the first, the second, and the third semiconductor patterns,
• wherein the forming of the active patterns includes:
• forming a first sacrificial layer and a first active layer on the substrate;
• forming a first mask pattern on a portion of the substrate;
• etching the first sacrificial layer and the first active layer partially using the first mask pattern as a mask to expose a portion of a top surface of the substrate;
• forming a semiconductor layer on the exposed portion of the top surface of the substrate, wherein a top surface of the semiconductor layer is coplanar with a top surface of the first active layer;
• forming staked sacrificial layers and active layers on the first active layer and the semiconductor layer, the active layers including an uppermost second active layer;
• forming a second mask pattern on a portion of the uppermost second active layer;
• and
• forming a trench using the second mask pattern as an etch mask, the trench defining the first active pattern and the second active pattern,
• wherein the first active pattern comprises a semiconductor layer disposed below and apart from the first channel pattern, and
• wherein the semiconductor layer comprises at least one of silicon or silicon phosphide.