Dual port SRAM cell and method of designing the same

A dual-port port static random access memory (SRAM) cell comprising:

• a plurality of P-type active patterns that are spaced apart from one another along a first direction, each of the plurality of P-type active patterns extending in a second direction perpendicular to the first direction and including at least one transistor, wherein the plurality of P-type active patterns comprises a first P-type active pattern, a second P-type active pattern, a third P-type active pattern, a fourth P-type active pattern, a fifth P-type active pattern and a sixth P-type active pattern which are sequentially arranged along the first direction;
• wherein a first cutting area is provided between the second P-type active pattern and a first boundary of the dual-port SRAM cell that extends along the first direction;
• a second cutting area is provided between the fifth P-type active pattern and a second boundary that is opposite to the first boundary and extends along the first direction;
• a first gate electrode provided on the second P-type active pattern and extending in the first direction;
• a second gate electrode provided on the fifth P-type active pattern, extending in the first direction, and spaced apart from the first gate electrode along the second direction;
• a third gate electrode provided on the third P-type active pattern, spaced apart from the second gate electrode along the first direction, and aligned with the second gate electrode along the first direction;
• and
• a fourth gate electrode provided on the fourth P-type active pattern, spaced apart from the first gate electrode along the first direction, and aligned with the first gate electrode along the first direction.

A bit cell comprising:

• a plurality of active patterns spaced apart from one another along a first direction, each of the plurality of active patterns extending in a second direction perpendicular to the first direction and having a constant width in the first direction between a first boundary of the bit cell and a second boundary of the bit cell opposite to the first boundary, wherein the first boundary and the second boundary extend in the first direction, and the plurality of active patterns comprises a first active pattern, a second active pattern, a third active pattern, a fourth active pattern, a fifth active pattern, a sixth active pattern, a seventh active pattern and an eighth active pattern that are sequentially arranged along the first direction;
• a first gate electrode provided on the second active pattern, the third active pattern and the fourth active pattern, and extending in the first direction;
• and
• a second gate electrode provided on the fifth active pattern, the sixth active pattern and the seventh active pattern, extending in the first direction, and spaced apart from the first gate electrode along the second direction,
• wherein a first cutting area is provided between the second active pattern and the first boundary,
• a second cutting area is provided between the seventh active pattern and the second boundary,
• the third active pattern and the sixth active pattern extend from the first boundary to the second boundary, and
• the constant width of the second active pattern in the first direction is different from the constant width of the third active pattern in the first direction.

A bit cell comprising:

• a plurality of active patterns spaced apart from one another along a first direction, each of the plurality of active patterns extending in a second direction perpendicular to the first direction and having a constant width in the first direction between a first boundary of the bit cell and a second boundary of the bit cell opposite to the first boundary, wherein the first boundary and the second boundary extend in the first direction, and the plurality of active patterns comprises a first active pattern, a second active pattern, a third active pattern, a fourth active pattern, a fifth active pattern, a sixth active pattern, a seventh active pattern and an eighth active pattern that are sequentially arranged along the first direction;
• a first gate electrode provided on the second active pattern, the third active pattern and the fourth active pattern, and extending in the first direction;
• and
• a second gate electrode provided on the fifth active pattern, the sixth active pattern and the seventh active pattern, extending in the first direction, and spaced apart from the first gate electrode along the second direction, and a fifth gate electrode provided on the first active pattern, spaced apart from the first gate electrode along the second direction, spaced apart from the second gate electrode in the first direction, and aligned with the second gate electrode along the first direction,
• wherein a first cutting area is provided between the second active pattern and the first boundary,
• a second cutting area is provided between the seventh active pattern and the second boundary,
• the third active pattern and the sixth active pattern extend from the first boundary to the second boundary,
• the first active pattern and the eighth active pattern extend from the first boundary to the second boundary,
• the first gate electrode extends in the first direction on the first active pattern, and
• the second gate electrode extends in the first direction on the eighth active pattern.

A dual-port static random access memory (SRAM) cell comprising:

• a plurality of active patterns spaced apart from one another along a first direction, each of the plurality of active patterns extending in a second direction perpendicular to the first direction and having a constant width in the first direction between a first boundary of the dual-port SRAM cell and a second boundary of the dual-port SRAM cell opposite to the first boundary, wherein the first boundary and the second boundary extend in the first direction, and the plurality of active patterns comprises a first active pattern, a second active pattern, a third active pattern and a fourth active pattern that are sequentially arranged along the first direction;
• a first gate electrode provided on the second active pattern, the third active pattern and the fourth active pattern, extending in the first direction, and spaced apart from the first active pattern along the second direction;
• and
• a second gate electrode provided on the third active pattern, extending in the first direction, and spaced apart from the first gate electrode along the second direction,
• wherein a cutting area is provided between the second active pattern and the first boundary, and
• the constant width of the second active pattern and the constant width of the third active pattern are different.