Method of and apparatus for controlling clock signal

An integrated circuit comprising:

• a first enabling transistor having a semiconductor channel connected to a first node and having a gate terminal configured to receive a first enabling signal;
• a second enabling transistor having a semiconductor channel connected to a second node and having a gate terminal configured to receive a second enabling signal which is a logical inverse of the first enabling signal;
• a plurality of branch-one transistors having semiconductor channels electrically connected in series between a first power supply and the first node, wherein each branch-one transistor has a gate terminal electrically connected to the second node, and wherein one of the branch-one transistors has a source terminal that is configured to be maintained at a constant supply voltage on the first power supply;
• and
• a plurality of branch-two transistors having semiconductor channels electrically connected in series between the first power supply and the second node, wherein each branch-two transistor has a gate terminal electrically connected to the first node, and wherein one of the branch-two transistors has a source terminal that is configured to be maintained at the constant supply voltage on the first power supply;
• and
• a clocking transistor having a semiconductor channel electrically connected to both a source terminal of the first enabling transistor and a source terminal of the second enabling transistor.

An integrated circuit comprising:

• a clocking transistor having a gate terminal configured to receive a first clock signal;
• a first enabling transistor having a semiconductor channel electrically connected between a drain terminal of the clocking transistor and a first node, wherein the first enabling transistor has a gate terminal configured to receive a first enabling signal;
• a second enabling transistor having a semiconductor channel electrically connected between a drain terminal of the clocking transistor and a second node, wherein the second enabling transistor has a gate terminal configured to receive a second enabling signal which is a logic inverse of the first enabling signal;
• a branch-one transistor having a semiconductor channel electrically connected between a first power supply and the first node and having a gate terminal electrically connected to the second node, wherein a source terminal of the branch-one transistor is configured to be maintained at a constant supply voltage on the first power supply, wherein the clocking transistor has a source terminal electrically connected to a second power supply;
• a branch-two transistor having a semiconductor channel electrically connected between the first power supply and the second node and having a gate terminal electrically connected to the first node, wherein a source terminal of the branch-two transistor is configured to be maintained at the constant supply voltage on the first power supply;
• a clock gating circuit having an output terminal configured to generate a gated clock signal and having a first input terminal configured to receive a latch output signal which is latched to a logic level of either a first node signal at the first node or a second node signal at the second node;
• and
• wherein each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor having an enhanced driving strength, the enhanced driving strength being larger than a default driving strength of another first-type transistor.