Semiconductor device and semiconductor system having the same

A semiconductor device comprising:

• at least one D flip-flop including a first D flip-flop,
• wherein the first D flip-flop includes:
• a first transmission gate gated by a transmission signal and configured to transmit input data of a first node to a second node;
• a master latch including:
• a first data inverter configured to invert the input data of the second node and output the input data as middle data to a third node;
• and
• a first feedback inverter connected to the first data inverter and configured to feed the middle data of the third node back to the second node;
• a second transmission gate gated by the transmission signal and configured to transmit the middle data of the third node to a fourth node;
• and
• a slave latch including:
• a second data inverter connected to the fourth node and configured to invert the middle data of the fourth node and output the middle data of the fourth node as output data to a fifth node;
• and
• a second feedback inverter connected to the fourth node and the fifth node and configured to feed the output data of the fifth node back to the fourth node, and
• wherein a pull-up operation of the second feedback inverter is disabled before a pull-down operation of the second transmission gate at the fourth node is enabled;
• and
• a clock buffer configured to receive a reference clock signal and generate an inverse clock signal and a delay clock signal from the reference clock signal as the transmission signal,
• wherein the second feedback inverter includes:
• a (2-1)-th PMOS feedback transistor including a first source/drain connected with a power supply voltage and a gate connected with the fifth node;
• and
• a (2-2)-th PMOS feedback transistor including a first source/drain connected with a second source/drain of the (2-1)-th PMOS feedback transistor, a second source/drain connected with the fourth node, and a gate connected with the reference clock signal.

A semiconductor system including a semiconductor device,

• wherein the semiconductor device includes:
• at least one flip-flop including a first flip-flop,
• wherein the first flip-flop includes:
• a first latch including a first data path receiving input data in response to a transmission signal and outputting middle data, and a first feedback path feeding the middle data back to the first data path;
• a second latch including a second data path receiving the middle data in response to the transmission signal and outputting output data, and a second feedback path feeding the output data back to the second data path,
• wherein at least one of the first feedback path and the second feedback path is disabled prior to enabling the first data path or the second data path;
• and
• a clock buffer configured to receive a reference clock signal and generate an inverse clock signal and a delay clock signal from the reference clock signal as the transmission signal,
• wherein the second feedback path includes a second feedback inverter including a (2-1)-th PMOS feedback transistor and a (2-2)-th NMOS feedback transistor each gated by the output data, a (2-2)-th PMOS feedback transistor gated by the reference clock signal, and a (2-1)-th NMOS feedback transistor gated by the inverse clock signal.