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US 12,224,747 B2Granted
Semiconductor device related to calibrating termination resistance
AssigneeSK hynix Inc.
InventorsChae Sung Lim, Jung Taek You, Saeng Hwan Kim, Sang Sic Yoon, Hong Joo Song
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Abstract
A semiconductor system includes a controller configured to apply a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device including a first rank and a second rank configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal.
Claims26
A semiconductor system comprising:
- a controller configured to transmit a command address, a first chip selection signal, and a second chip selection signal;
- and
- a semiconductor device configured to receive the command address, the first chip selection signal, and the second chip selection signal, the semiconductor device including a first rank and a second rank that are configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal,
- wherein the first rank calibrates the termination resistance of the first rank to a target resistance, based on the command address and the first chip selection signal when a write operation on the first rank is performed, and
- wherein the second rank calibrates the termination resistance of the second rank to a dynamic resistance, based on the command address and the second chip selection signal when a write operation on the second rank is performed.
2 more elements
A semiconductor device comprising:
- a first rank configured to calibrate a first termination resistance to a target resistance when a write command is input through a command address in a state in which a first chip selection signal set to have a first voltage level is generated;
- and
- a second rank configured to calibrate a second termination resistance to a target resistance when the write command is input through the command address in a state in which a second chip selection signal set to have a first voltage level is generated,
- wherein the second rank calibrates the second termination resistance to the dynamic resistance according to the second chip selection signal set to have the second voltage level when a write operation on the first rank is performed.
1 more element
A semiconductor system comprising:
- a controller configured to transmit a command address, a first chip selection signal, a second chip selection signal, and a third chip selection signal;
- and
- a semiconductor device configured to receive the command address, the first chip selection signal, the second chip selection signal, and the third chip selection signal, the semiconductor device including a first rank, a second rank, and a third rank that are configured to calibrate each termination resistance, based on the command address, the first chip selection signal, the second chip selection signal, and the third chip selection signal,
- wherein the first rank calibrates the termination resistance of the first rank to a target resistance, based on the command address and the first chip selection signal when a write operation on the first rank is performed,
- wherein the second rank calibrates the termination resistance of the second rank to a first dynamic resistance, based on the second chip selection signal when the write operation on first second rank is performed, and
- wherein the third rank calibrates the termination resistance of the third rank to a second dynamic resistance, based on the third chip selection signal when the write operation on the first rank is performed.
3 more elements
Dependencies are inferred from the claim text.