Multiple-stage Doherty power amplifiers implemented with multiple semiconductor technologies

An amplifier, comprising:

• a first radio frequency (RF) input terminal;
• a first driver amplifier module including a second RF input terminal electrically connected to the first RF input terminal, a first RF output terminal, and a first driver amplifier, wherein the first driver amplifier includes a first heterojunction bipolar transistor (HBT) a second HBT, and a bias control circuit, wherein the first HBT is coupled to the second HBT in a cascode configuration and wherein the bias control circuit is coupled to a base of the first HBT, and wherein the first driver amplifier includes a first variable capacitance, a first terminal of the first variable capacitance is electrically connected to a collector of the second HBT, and a second terminal of the first variable capacitance is electrically connected to the base of the first HBT;
• and
• a first power amplifier module including a third RF input terminal electrically connected to the first RF output terminal, a second RF output terminal, and a first power transistor coupled between the third RF input terminal and the second RF output terminal.

A device, comprising:

• an integrated circuit (IC) die, wherein the IC die includes a silicon germanium (SiGe) substrate, a first RF signal input terminal, a first RF signal output terminal, a first amplification path between the first RF signal input terminal and the first RF signal output terminal, a second RF signal input terminal, a second RF signal output terminal, and a second amplification path between the second RF signal input terminal and the second RF signal output terminal, wherein the first amplification path includes a first heterojunction bipolar transistor (HBT) coupled between the first RF signal input terminal and the first RF signal output terminal, the second amplification path includes a second heterojunction bipolar transistor (HBT) coupled between the second RF signal input terminal and the second RF signal output terminal, wherein a first bias control circuit is coupled to a first base of the first HBT, and wherein a second bias control circuit is coupled to a second base of the second HBT, and wherein the IC die includes a first variable capacitance, a first terminal of the first variable capacitance is electrically connected to a collector of the second HBT, and a second terminal of the first variable capacitance is electrically connected to the base of the first HBT;
• a first power transistor die connected between the RF signal input terminal and the first RF signal output terminal;
• and
• a second power transistor die connected between the second RF signal input terminal and the second RF signal output terminal.