Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit

A three-dimensional (3D) integrated circuit (IC) package, comprising:

• a first IC die comprising a first substrate at a back side of the first IC die;
• a second IC die stacked at the back side of the first IC die and facing the first substrate;
• a hybrid bonding (HB) structure bonding the first IC die and the second IC die, the HB structure having a HB region surrounding the HB structure;
• and
• a transistor fabricated in the first substrate, wherein the transistor is electrically connected to the HB structure, the transistor is fabricated within the HB region surrounding the HB structure, and wherein no functional cell is fabricated within the HB region.

A method, comprising:

• providing a first IC die comprising a first substrate at a back side of the first IC die;
• fabricating a through-substrate via (TSV) through the first substrate, the TSV comprising a TSV cell having a TSV cell boundary surrounding the TSV;
• fabricating an electrostatic discharge (ESD)_protection module in the first substrate, wherein the ESD protection module is electrically connected to the TSV, wherein the ESD protection module is within the TSV cell boundary surrounding the TSV, and wherein no functional cell is fabricated within the TSV cell boundary;
• providing a second IC die at a front side of the first IC die;
• and
• bonding the second IC die to the first IC die, the first IC die and the second IC die being electrically connected through the TSV.