Self-aligned gate endcap (SAGE) architectures with vertical sidewalls

An integrated circuit structure, comprising:

• a first semiconductor fin having sidewalls along a length of the first semiconductor fin, each of the sidewalls of the first semiconductor fin tapering outwardly from a distal end of the first semiconductor fin toward a substrate from which the first semiconductor fin extends;
• a second semiconductor fin having sidewalls along a length of the second semiconductor fin, each of the sidewalls of the second semiconductor fin tapering outwardly from a distal end of the second semiconductor fin toward the substrate;
• a trench isolation structure laterally between the first semiconductor fin and the second semiconductor fin, the trench isolation structure surrounding an end of a cut fin portion;
• a first gate endcap isolation structure between the first semiconductor fin and the second semiconductor fin, the first gate endcap isolation structure having a length parallel with the lengths of the first and second semiconductor fins, the first gate endcap isolation structure having a first substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the first semiconductor fin, and a second substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the second semiconductor fin, and wherein the first gate endcap isolation structure is recessed into the trench isolation structure, the first gate endcap isolation structure having a first width;
• a second gate endcap isolation structure, the second gate endcap isolation structure having a length parallel with the lengths of the first and second semiconductor fins, the second gate endcap isolation structure having a second width greater than the first width;
• and
• at least one gate electrode covering the distal end of the first semiconductor fin and the distal end of the second semiconductor fin, the at least one gate electrode in contact with the first and second gate endcap isolation structures, wherein the second gate endcap isolation structure is positioned at a lateral side of the at least one gate electrode.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, the integrated circuit structure including:
• a semiconductor fin having sidewalls along a length of the semiconductor fin, the sidewalls tapering outwardly from a distal end of the semiconductor fin toward a substrate from which the semiconductor fin extends;
• a trench isolation structure laterally adjacent to at least a portion of the semiconductor fin;
• a first gate endcap isolation structure having a length parallel with the length of the semiconductor fin, the first gate endcap isolation structure having a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin with the trench isolation structure therebetween, the first gate endcap isolation structure extending into the trench isolation structure, the first gate endcap isolation structure having a first width;
• a second gate endcap isolation structure having a length parallel with the length of the semiconductor fin, the second gate endcap isolation structure having a substantially vertical sidewall laterally facing one of the outwardly tapering sidewalls of the semiconductor fin with the trench isolation structure therebetween, the second gate endcap isolation structure extending into the trench isolation structure, the second gate endcap isolation structure having a second width greater than the first width;
• and
• a gate electrode in direct physical contact with the first and second gate endcap isolation structures, the second gate endcap isolation structure at a lateral side of the gate electrode.