Method and system for control of sidewall orientation in vertical gallium nitride field effect transistors

A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising:

• providing the III-nitride substrate comprising an alignment reference structure, wherein the alignment reference structure defines a reference direction on the III-nitride substrate;
• determining <1210> directions of the III-nitride substrate;
• computing a difference between the reference direction and the <1210> directions to define a correction factor;
• aligning a mask with respect to the III-nitride substrate using correction factor;
• forming a mask layer including a plurality of mask patterns;
• providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and defining a channel region extending between a source region and a drain region;
• forming a plurality of gate regions in contact with the plurality of gate interface regions;
• forming a gate electrode coupled to the plurality of gate regions;
• forming a source electrode coupled to the source region;
• and
• forming a drain electrode coupled to the drain region.