Power device with partitioned active regions

A semiconductor device having a first surface and a second surface opposite the first surface, the semiconductor device comprising:

• a substrate;
• an epitaxial layer formed over the substrate;
• a plurality of active regions disposed over the substrate and formed in the epitaxial layer, the plurality of active regions having a first total area;
• and
• a plurality of cells of an active device comprising a silicon carbide Metal-Oxide-Semiconductor Field Effect Transistor, the plurality of cells respectively disposed in the plurality of active regions;
• a plurality of control pads disposed over the first surface and respectively electrically coupled to gate electrodes of the plurality of cells;
• a plurality of source pads disposed over the first surface and respectively electrically coupled to source electrodes of the plurality of cells;
• a drain contact disposed over the second surface and electrically coupled to drain electrodes of the plurality of cells;
• one or more inactive regions disposed over the substrate and between respective pairs of the active regions, the one or more inactive regions having a second total area,
• wherein the second total area is greater than or equal to 1.5 times the first total area,
• wherein the active regions are disposed in a plurality of rows and a plurality of columns, and
• wherein a first active region in a first row of the plurality of rows is offset in a direction along the row from a second active region in a second row of the plurality of rows by an amount different from the center-to-center distance between adjacent active regions in the first row, the second row being adjacent to the first row.

A semiconductor device having a first surface and a second surface opposite the first surface, the semiconductor device comprising:

• a substrate;
• an epitaxial layer formed over the substrate;
• a plurality of active regions disposed over the substrate and formed in the epitaxial layer, the plurality of active regions having a first total area;
• and
• a plurality of cells of an active device comprising a silicon carbide Metal-Oxide-Semiconductor Field Effect Transistor, the plurality of cells respectively disposed in the plurality of active regions;
• a plurality of control pads disposed over the first surface and respectively electrically coupled to gate electrodes of the plurality of cells;
• a plurality of source pads disposed over the first surface and respectively electrically coupled to source electrodes of the plurality of cells;
• a drain contact disposed over the second surface and electrically coupled to drain electrodes of the plurality of cells;
• one or more inactive regions disposed over the substrate and between respective pairs of the active regions, the one or more inactive regions having a second total area,
• wherein the second total area is greater than or equal to 1.5 times the first total area, and
• wherein the active regions are disposed over a plurality of respective substrate mesas having heights greater than portions of the substrate under the inactive regions.