Gate contact structure for a trench power MOSFET with a split gate configuration

An integrated circuit transistor, comprising:

• a semiconductor substrate providing a drain;
• a first doped region buried in the semiconductor substrate providing a body;
• a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent the first doped region;
• a trench extending into the semiconductor substrate and passing through the first and second doped regions;
• a polyoxide region within the trench;
• a polygate region within the trench, said polygate region comprising:
• a first gate lobe on a first side of the polyoxide region and a second gate lobe on a second side of the polyoxide region opposite said first side;
• an insulating layer extending over the first doped region and trench;
• and
• a pair of gate contacts for said trench, said pair of gate contacts comprising:
• a first gate contact extending through the insulating layer and into the first gate lobe;
• and
• a second gate contact extending through the insulating layer and into the second gate lobe;
• wherein the polyoxide region is aligned with a center of the trench and wherein a center of each of the first and second gate contact is located between a center of the corresponding first and second gate lobe and the center of the trench and in contact with the polyoxide region.

An integrated circuit transistor device, comprising:

• a semiconductor substrate providing a drain;
• a first doped region buried in the semiconductor substrate providing a body;
• a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent the first doped region;
• a trench extending into the semiconductor substrate and passing through the first and second doped regions;
• an insulated polysource region within the trench;
• a polyoxide region within the trench and aligned with said insulated polysource region, wherein said polyoxide region includes void;
• a first insulated gate lobe on a first side of the polyoxide region;
• a second insulated gate lobe on a second side of the polyoxide region opposite said first side;
• a first gate contact extending into the first gate lobe, said first gate contact laterally offset from a longitudinal center of the trench such that a depth of the first gate contact does not reach said void;
• and
• a second gate contact extending into the second gate lobe, said second gate contact laterally offset from the longitudinal center of the trench such that a depth of the second gate contact does not reach said void.

An integrated circuit transistor device, comprising:

• a semiconductor substrate providing a drain;
• a first doped region buried in the semiconductor substrate providing a body;
• a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent the first doped region;
• a trench extending into the semiconductor substrate and passing through the first and second doped regions;
• a polyoxide region within the trench;
• a polygate region within the trench, said polygate region comprising:
• a first gate lobe on a first side of the polyoxide region, a second gate lobe on a second side of the polyoxide region opposite said first side and a bridge region extending over the polyoxide region and electrically coupling the first insulated gate lobe to the second insulated gate lobe;
• an insulating layer extending over the first doped region and trench;
• and
• a gate contact extending through the insulating layer and into the first gate lobe for said trench, and wherein said bridge region laterally extends away from said gate contact, wherein the gate contact has a length extending parallel to a longitudinal direction of the trench that is greater than a width perpendicular to the length.

An integrated circuit transistor device, comprising:

• a semiconductor substrate providing a drain;
• a first doped region buried in the semiconductor substrate providing a body;
• a second doped region in the semiconductor substrate providing a source, wherein the second doped region is adjacent the first doped region;
• a trench extending into the semiconductor substrate and passing through the first and second doped regions;
• a polyoxide region within the trench;
• a polygate region within the trench, said polygate region comprising:
• a first gate lobe on a first side of the polyoxide region, a second gate lobe on a second side of the polyoxide region opposite said first side and a bridge region extending over the polyoxide region and electrically coupling the first insulated gate lobe to the second insulated gate lobe;
• an insulating layer extending over the first doped region and trench;
• and
• a gate contact extending through the insulating layer and into the first gate lobe for said trench, and wherein said bridge region laterally extends away from said gate contact;
• wherein the polyoxide region includes a void, and wherein the gate contact is offset from the void in a lateral direction of the trench.