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US 12,224,335 B2Granted
Semiconductor device and fabrication method thereof
AssigneeUnited Microelectronics Corp.
InventorChing-Chung Yang
Life of this patent
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Abstract
A semiconductor device includes a substrate of first conductivity type; a first heavily doped region and a second heavily doped region of second conductivity type spaced apart from the first heavily doped region, located in the substrate; a channel region in the substrate and between the first heavily doped region and the second heavily doped region; a gate disposed on the channel region; a hard mask layer covering a top surface and a sidewall of the gate; and a spacer disposed on a sidewall of the hard mask layer.
Claims14
A semiconductor device, comprising:
- a substrate of a first conductivity type;
- a first heavily doped region of a second conductivity type in the substrate;
- a second heavily doped region of the second conductivity type spaced apart from the first heavily doped region, located in the substrate;
- a channel region in the substrate and between the first heavily doped region and the second heavily doped region;
- a gate disposed on the channel region;
- a hard mask layer covering a top surface and a sidewall of the gate, wherein the gate is a polysilicon gate, and wherein the hard mask layer is in direct contact with the polysilicon gate, wherein the hard mask layer is a bi-layer structure comprising a silicon nitride lower layer and a silicon oxide upper layer, wherein a sidewall of the silicon nitride lower layer is flush with a sidewall of the silicon oxide upper layer;
- and
- a spacer disposed on a sidewall of the hard mask layer, wherein the spacer is in direct contact with the sidewall of the silicon nitride lower layer and the sidewall of silicon oxide upper layer.
5 more elements
A method of fabricating a semiconductor device, comprising:
- providing a substrate of a first conductivity type;
- forming a first heavily doped region of a second conductivity type in the substrate;
- forming a second heavily doped region of the second conductivity type spaced apart from the first heavily doped region, in the substrate;
- forming a channel region in the substrate and between the first heavily doped region and the second heavily doped region;
- forming a gate on the channel region;
- forming a hard mask layer covering a top surface and a sidewall of the gate, wherein the gate is a polysilicon gate, and wherein the hard mask layer is in direct contact with the polysilicon gate, wherein the hard mask layer is a bi-layer structure comprising a silicon nitride lower layer and a silicon oxide upper layer, wherein a sidewall of the silicon nitride lower layer is flush with a sidewall of the silicon oxide upper layer;
- and
- forming a spacer on a sidewall of the hard mask layer, wherein the spacer is in direct contact with the sidewall of the silicon nitride lower layer and the sidewall of silicon oxide upper layer.
5 more elements
Dependencies are inferred from the claim text.